Implementation and Verification of Synchronous FIFO using System Verilog Verification Methodology
DOI:
https://doi.org/10.22385/jctecs.v2i0.19Keywords:
System Verilog, SoC, Design under test (DUT), RTL, Testbench, IntegratedAbstract
Developing complex nature of patterns & concurrency of Integrated Circuits has made conventional coordinated test- benches an unworkable answer for testing. Nowadays, testing as a word has been substituted with check. Confirmation specialists need to guarantee what goes to the plant for assembling is an exact representation of the specification of configuration. Verification is the maximum time consuming stage in the whole design process, thus it has become a necessity to minimize the time required to encounter the confirmation necessities. The relentless growth in the complexity of the system, has led to the requirement of a more advanced, well organized and automated approach for creating verification environments. As the designs gets complex, the probability of occurrence of bugs increases. This nеcеssitatеd the introduction of the verification phase for verifying the functionality of the IC and to detect the bugs at an early stage. In this paper, the synchronous FIFO design is verified using System Verilog Verification Environment.
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