Low Power, Area Efficient Dynamic Voltage Comparator With Reduced Activity Factor

Amol Dnyandev Shinde, Manish Sharma

Abstract


This paper introduces the design of dynamic voltage comparator with reduced activity factor for low voltage and low power operation. An analysis of CMOS circuit power consumption is presented along with implication of activity factor on power consumption. A new architecture based on theoretical analysis for a dynamic comparator is proposed. The proposed comparator has a reduced activity factor and thus it consumes less power and it also has reduced transistor count over the design of double tail dynamic comparator which gives the area efficiency. The proposed design compares small input differential voltages efficiently with low power consumption. All circuit designs are simulated in Tanner tools V16 with 90nm CMOS technology. Simulation result shows that proposed design has less active and standby power consumption.

Full Text:

PDF

References


A. Hajimiri and R. Heald, “Design issues in cross coupled inverter sense amplifier,” IEEE Circuits and Systems, vol. 2, pp. 149-152, 1998.

A. Mesgarani, M. N. Alam, F. Z. Nelson, and S. U. Ay, “Supply boosting technique for designing very low voltage mixed-signal circuits in standard CMOS,” IEEE Int. Midwest Symp. Circuits Syst. Dig. Tech. Papers, pp. 893–896 Aug. 2010.

B. Goll and H. Zimmermann, “A comparator with reduced delay time in 65-nm CMOS for supply voltages down to 0.65,” IEEE Trans. Circuit Syst. II, Exp. Briefs, vol. 56, no. 11, pp. 810–814, Nov. 2009.

B. Goll and H. Zimmermann, “Low-power 600MHz comparator for 0.5V supply voltage in 0.12 μm CMOS,” IEEE Electron. Lett., vol. 43, no. 7, pp. 388–390, Mar. 2007.

B. J. Blalock, “Body-driving as a low-voltage analog design technique for CMOS technology,” IEEE Southwest Symp. Mixed-Signal Design, pp. 113–118, Feb. 2000.

B. Wicht, T. Nirschl, and D. Schmitt-Landsiedel, “Yield and speed optimization of a latch-type voltage sense amplifier,” IEEE J. Solid State Circuits, vol. 39, no. 7, pp. 1148–1158, Jul. 2004.

D. Shinkel, E. Mensink, E. Klumperink, E. van Tuijl, and B. Nauta, “A double-tail latch-type voltage sense amplifier with 18ps Setup+Hold time,” IEEE Int. Solid-State Circuits Conf., Dig. Tech. Papers, pp. 314–315, Feb. 2007.

D. Xu, S. Xu and G. Chen, “High-speed low-power and low-power supply voltage dynamic comparator,” IEEE Electron. Lett., vol. 51, no. 23, pp. 1914-1916, Nov. 2015.

M. Maymandi-Nejad and M. Sachdev, “1-bit quantiser with rail to rail input range for sub-1V Δ modulators,” IEEE Electron. Lett., vol. 39, no. 12, pp. 894–895, Jan. 2003.

N. Bala, B. Abdul and B. Nagendra, “Domino logic based high speed dynamic comparator,” IEEE Int. innovations in information embedded and comm. Systems, 2015.

Neil weste and David Harris, “CMOS VLSI design a circuits and systems perspective”, New York, Addison-Wesley, fourth edition.

S. Gawhare and A. Gaikwad, “Area and power efficient high speed voltage comparator,” Int. automatic control and dynamic optimization techniques, pp. 198-201, 2016.

S. Haung, L. He, Y. Chou and F. Lin, “A 288-uW 6-GHz hybrid dynamic comparator with 54-ps delay in 40-nm CMOS,” IEEE, 2016.

S. Mashhadi and R. Lotfi, “Analysis and design of a low-voltage low power double tail comparator,” IEEE Trans. VLSI Systems, vol. 22, no. 2, Feb. 2014.

S. U. Ay, “A sub-1 volt 10-bit supply boosted SAR ADC design in standard CMOS,” Int. J. Analog Integr. Circuits Signal Process., vol. 66, no. 2, pp. 213–221, Feb. 2011.




DOI: http://dx.doi.org/10.22385/jctecs.v12i0.167